1. Field of the Invention
The present invention relates generally to memory cell structures employed within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for fabricating memory cell structures employed within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices, and over which are formed patterned conductor layers which are separated by dielectric layers.
Common in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, is the use and the fabrication of memory cell structures, and in particular dynamic random access memory (DRAM) cell structures. Dynamic random access memory (DRAM) cell structures typically comprises a field effect transistor (FET) device formed within and upon a semiconductor substrate, where one of a pair of source/drain regions within the field effect transistor (FET) device has formed thereover and electrically connected therewith a storage capacitor. Within a dynamic random access memory (DRAM) cell structure, a gate electrode of the field effect transistor (FET) device serves as a wordline which provides a switching function for charge introduction into and retrieval from the storage capacitor, while the other of the pair of source/drain regions within the field effect transistor (FET) device serves as a contact for a bitline conductor stud which introduces or retrieves charge with respect to the storage capacitor.
While the dynamic random access memory (DRAM) cell structure has clearly become ubiquitous in the art of semiconductor integrated circuit microelectronic memory fabrication, and is thus essential in the art of semiconductor integrated circuit microelectronic fabrication, the dynamic random access memory (DRAM) cell structure is nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic memory fabrication.
In that regard, as semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor device and patterned conductor layer dimensions have decreased, it has become increasingly difficult in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to readily form dynamic random access memory (DRAM) cell structures with enhanced performance.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to provide methods and materials through which there may be readily formed, with enhanced performance, dynamic random access memory (DRAM) cell structures.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for forming, with desirable properties, dynamic random access memory (DRAM) cell structures.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Dennison, in U.S. Pat. No. 5,206,183 (a method for forming a capacitor under bitline (CUB) dynamic random access memory (DRAM) cell structure for use within a semiconductor integrated circuit microelectronic memory fabrication, with improved fabrication alignment, by employing when fabricating the capacitor under bitline (CUB) dynamic random access memory (DRAM) cell structure several sacrificial polyimide masking layers); and (2) Lee et al., in U.S. Pat. No. 6,246,087 (a method for forming a capacitor over bitline (COB) dynamic random access memory (DRAM) cell structure for use within a semiconductor integrated circuit microelectronic memory fabrication, with enhanced fabrication reliability, by forming within the capacitor over bitline (COB) dynamic random access memory (DRAM) cell structure a bitline stud layer while employing a multi-step masking method).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for forming, with enhanced performance, dynamic random access memory (DRAM) cell structures.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a method for forming a dynamic random access memory (DRAM) cell structure within a semiconductor integrated circuit microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the dynamic random access memory (DRAM) cell structure is formed with enhanced performance.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a memory cell structure, and a memory cell structure fabricated employing the method.
To practice the method of the present invention, there is first provided a semiconductor substrate. There is then formed within and upon the semiconductor substrate a field effect transistor (FET) device comprising a gate dielectric layer formed upon the semiconductor substrate, a gate electrode formed upon the gate dielectric layer and a pair of source/drain regions formed into the semiconductor substrate and separated by the gate electrode. There is then formed over the field effect transistor (FET) device, and electrically connected with one of the pair of source/drain regions, a storage capacitor comprising a capacitor node layer connected with the one of the pair of source/drain regions, a capacitor dielectric layer formed upon the capacitor node layer and a capacitor plate layer formed upon the capacitor dielectric layer. There is also formed over the field effect transistor (FET) device and electrically connected with the other of the pair of source/drain regions a bitline stud layer laterally separated from and rising above the storage capacitor, where at a minimum storage capacitor to bitline stud layer separation distance the capacitor plate layer is further separated from the bitline stud layer than the capacitor node layer.
The method of the present invention contemplates a dynamic random access memory (DRAM) cell structure fabricated in accord with the method of the present invention.
The present invention provides a method for forming a dynamic random access memory (DRAM) cell structure within a semiconductor integrated circuit microelectronic fabrication, wherein the dynamic random access memory (DRAM) cell structure is readily formed with enhanced performance.
The present invention realizes the foregoing object within the context of a capacitor under bitline (CUB) dynamic random access memory (DRAM) cell structure by providing, at a minimum storage capacitor to bitline stud layer separation distance, that a capacitor plate layer is further separated from a bitline stud layer than a capacitor node layer within the capacitor under bitline (CUB) dynamic random access memory (DRAM) cell structure.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are generally known in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of specific process orderings and specific materials limitations to provide the method for fabricating a memory cell structure in accord with the present invention. Since it is thus at least in part a specific process ordering and specific material limitations which provide at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.